1. Field of the Invention
The present invention pertains to the fields of integrated circuit (IC) design. More particularly, this invention relates to electronic design automation (EDA) tools employed to assist placement and routing of an IC design.
2. Background
Logic equivalence identifies classes of permutable pins (or nets) with an IC design. In application Ser. No. 09/118,225, digital circuit layout techniques including in particular techniques for identifying logic equivalency in an IC design were disclosed. In application Ser. No. 09/470,540, additional techniques for identifying logic equivalency in an IC design were disclosed.
Such pins (or nets) may be swapped without impacting the logic of the IC design. In particular once identified these pins (or net) may be swapped to reduce wire length, improve circuit timing or reduce routing congestion, when placing and routing an IC design. Thus, an improved machine implemetable place and route technique that leverages on the identified logic equivalents, when placing and routing an IC design is desired.
At least one EDA tool is provided with first and second plurality of programming instructions. The first plurality of programming instructions are designed to determine equivalent logic in an IC design, and the second plurality of programming instructions are designed to place and route the IC design. The place and route operation includes performance of at least one place and route operation selected from a group of place and route operations consisting of choosing coupling assignments for nets and logically equivalent input pins of the IC design, and choosing coupling assignments for logically equivalent output pins and loads of the IC design.
In one embodiment, coupling assignments are chosen to minimize total wire length of an IC design. The coupling assignment selection problem is formulated as a bi-partite matching problem, more specifically, a weighted matching problem. Manhattan distances are employed in weight assignments, and penalty costs are added for congested areas. In one embodiment, coupling assignments are chosen to minimize selected total delay times. The coupling assignment selection problem is also formulated as a bi-partite matching problem, more specifically, a max-min matching problem. Slack times are determined in accordance with arrival and required times.